In this post, we are going to see the clock divide by 3 circuit and implementation using Verilog RTL.
Refer the below circuit, the circuit will work as clock frequency divider by 3, In this case 50 MHz input clock is used as reference clock frequency, and the output of the circuit is 16.6 MHz frequency with 50% duty cycle. This value is equal to the divide by 3 of 50.
Divide by 3 circuit uses 3 flip flops, the first two flip flops are positive edge triggered and the 3rd flip flop is negative edge triggered. The inverted output of the first two flip flops (q_bar) will be AND ed and and given to the input of the first flip flop. The output of the second flip flop will be the input to the third flip flop. The final divide by 3 output will be OR value of second and third flip flops output.
Verilog RTL:
`timescale 1ns / 1ps
module clk_div(
input clk,
output wire clk_out
);
// Internal signals declaration
reg q_reg = 1'b0;
reg q_reg1 = 1'b0;
reg q_reg2 = 1'b0;
always @ (posedge clk) begin
q_reg <= ~q_reg & ~q_reg1;
q_reg1 <= q_reg;
end
always @ (negedge clk) begin
q_reg2 <= q_reg1;
end
assign clk_out = q_reg1 | q_reg2;
endmodule
Testbench:
`timescale 1ns / 1ps
module tb_clk_div(
);
parameter CLK_PERIOD = 20; // 50 MHz
reg clk;
wire clk_out;
clk_div dut_inst (
.clk ( clk ),
.clk_out ( clk_out )
);
// registers initialization
initial begin
clk = 1'b0;
end
// clk generation //
always begin
#(CLK_PERIOD/2);
clk = 1'b0;
#(CLK_PERIOD/2);
clk = 1'b1;
end
endmodule
Simulation waveform:
The design is synthesized using Vivado IDE, and the simulation results are taken using Vivado ISE.
Generally the clock divider by 3 will be asked in the interview rather used in the design practically, because mostly of designers are using PLL block directly to divide the clock, especially in Xilinx FPGA advanced DCM blocks are available to do the following operation division, multiplication, etc..
Thanks,
